Local area networks (LAN) utilize a clock recovery scheme to extract a clock signal from the data transmitted between stations over the network. The recovered clock signal is then used to properly synchronize the operations performed on the incoming data, e.g., sampling and decoding of the data.
As data rates for local area networks increase, the clock recovery module (CRM) used to recover clock and data from the incoming data stream increases in power consumption and area. For example, on a 0.35 um, 3V process, a currently available 10BT CRM requires 150 sq mils area and draws about 6 mW of power. A currently available 100BX CRM requires about 1.5K sq mils area, and draws about 50 mW of power. Based on these requirements, a 1000BX CRM would be very hard to implement with such a process.
Current 1000BX CRM's are based on BiCMOS processes, which are expensive and draw a lot of power (1 W is typical for currently available 1000BX CRMs). The large power consumption makes integration of multiple clock recovery channels onto a single die extremely difficult, and makes integration of a clock recovery channel with an application specific integrated circuit (ASIC) unattractive. This is a significant limitation because integration of multiple CRM's onto a single die would make fully integrated gigabit repeaters, buffered distributors and switches possible.
This problem has been addressed by the use of clock recovery modules using interleaved phase detectors. For example, to recover 1000 mb data (a 1.25 mhz embedded clock), a 15 phase voltage controlled oscillator (VCO) operating at 250 mhz could be used. Three consecutive VCO phases would be compared to every 5th bit of data in such a way that all bits are compared to a phase (i.e., phase 1-3 compared to 1st bit, phase 4-6 to 2nd, . . . , phase 13-15 to 5th, phase 1-3 to 6th, etc.). Five phase detectors are used, with three input phases per phase detector. Phases 1-3 sample a data bit, and phase information and recovered data are extracted. Prior approaches have then used a charge pump per phase detector to create five charging/discharging currents to modify the control voltage of a single filter. The filter voltage is then used to adjust the VCO frequency, bringing the 15 VCO phases into phase with the input data stream transitions. A data aligner circuit brings the five recovered data streams in phase with each other, and one of the VCO phases is used as the recovered clock. This provides a 5-bit wide vector of recovered data with a 250 mhz RXC.
The above explanation describes a specific case of how an interleaved phase detector CRM can recover an Xmhz clock from a data stream using 3*N phases of a Ymhz VCO clock, where X/Y=N. One prior solution ("A 622 Mb CMOS Clock Recovery PLL with Time-Interleaved Phase Detector Array", ISSCC96 Session 12/Serial Data Communications) reports power consumption of 200 mW and an area of 1100 sq mils using a 5V, 0.8 um process. Another prior solution ("A 0.8 um CMOS 2.5 Gb/s Oversampled Receiver for Serial Links", ISSCC96/SESSION12) reports power consumption of 1 W and an area of 14K sq mils.
A phase picker clock recovery architecture has been used to increase the phase resolution of a recovered clock signal. A phase picker architecture adjusts the phase of the recovered clock in response to a filtered phase error detected by a phase detector, which compares the phase of the recovered clock signal with the incoming data. The phase of the recovered clock signal is then adjusted by selecting a different phase of N available phases provided by a clock generation module. An N:1 phase multiplexer is used to perform the phase selection. A phase picker clock recovery loop of a given order has essentially the same response as a VCO based clock recovery loop of that order plus one.
Advantages of a phase picker type loop include: loop parameters are independent of PVT, the CRM is totally digital, it allows sharing of multiple CRM's among a single CGM.
What is desired is an apparatus for recovering a clock signal from a transmitted data stream using a single clock recovery channel capable of operating at a 1000 mb/sec data rate to extract a clock signal from the data transmitted between two stations or nodes of a local area network, and which reduces the surface area and power required for currently available architectures.